Memory devices may include an array of memory cells that store data. The memory cells may be coupled to wordlines and bitlines. Sense circuitry may be electrically coupled to the array to read the data. In particular, the sense circuitry may be configured to sense current flowing through the bitlines. Based on the sensing, the sense circuitry may generate output signals indicative of the logic levels of the data being stored.
The sense circuitry may include a plurality of sense amplifier circuits. Each sense amplifier circuit may be coupled to a respective one of the bitlines, which in turn is coupled to a memory cell. A sense amplifier circuit may be configured to generate an output signal indicative of a logic level of the data stored in the memory cell to which it is coupled. Sense amplifier circuits coupled to multiple bitlines may be configured to operate simultaneously in order for data stored in multiple memory cells to be sensed simultaneously. To that end, it may be desirable for the sense amplifier circuits to output their respective output signals at the same time or as close to the same time as possible. However, due to inherent mismatches, such as mismatches in transistor oxide thicknesses, the sense amplifier circuits may output their respective output signals at different times. Thus, sense amplifier calibration processes that can calibrate sense amplifier circuits to output their respective output signals more closely in time may be desirable.